1. Field of the Invention
The present invention relates to a memory device employing an open bit line architecture, and more particularly to a memory device for matching data topology in case of repairing a defective cell of a memory block, and a method thereof.
2. Description of Related Art
In a memory device, an open bit line cell structure is a configuration in which sense amplifiers are formed between bit line pairs (BL, /BL). Another configuration is a folded bit line cell structure in which the bit line pairs (BL, /BL) are formed side by side on one side of the sense amplifiers.
Memory cells having the open bit line architecture are arranged at all intersections where word lines WLs cross bit lines BLs. Such an arrangement can improve the density of the memory cells, thereby reducing an area occupied by the memory device. Compared to the folded bit line structure, the open bit line cell structure has a greater density and reduced cell area.
FIG. 1 is a block diagram illustrating a conventional memory device employing an open bit line architecture.
Bit line pairs (BL, /BL) are respectively placed at both sides of a sense amplifier block 130. Memory cell blocks 110 and 120 are placed at all intersections of the bit line pairs (BL, /BL) and word lines WLs.
The memory blocks 110 and 120 in the memory device include a normal memory cell block(s) and a spare memory cell block(s) for replacing a defective memory cell with redundant memory cell(s).
In addition, the memory device further includes row decoders 140 for decoding an external address to drive a normal word line in a corresponding memory cell block, spare row decoders 150 for storing information about defective addresses and driving a spare word line so as to repair a defective cell, and a column select switch CSW for providing data amplified by the sense amplifier 130 into local data line pairs (LDL, /LDL).
The memory cell blocks 110 and 120 illustrated in FIG. 1 may be identified using specified block address information. For example, when the eighth bit of an external row address provided from an external source is ‘0’, an even numbered memory cell block 110 is selected. And when the eighth bit of the external row address is ‘1’, an odd numbered memory cell block 120 is selected.
In general, a memory cell formed at an intersection of a bit lines BL and a word lines WL is defined as a ‘true cell’, and a memory cell formed at an intersection of a bit lines /BL and a word line WL is defined as a ‘complement cell’.
The true cell stores data having a data topology identical to the data topology of data provided from an external source. The complement cell stores data having a reverse data topology of the data provided from the external source.
In the memory device employing an open bit line structure, data topology in the even numbered memory cell block 110 has a data sequence of C-T-C-T cells, whereas the data topology in the odd numbered memory cell block 120 has a data sequence of T-C-T-C cells. Hereinafter, the data topology is referred to as the order of data input/output or the data input sequence/data output sequence. Namely, the even numbered memory cell block has different data topology from the odd numbered memory cell block.
As a result, a defective cell in a first memory cell block may be replaced with a normal cell in the first memory cell block since the data topology is the same within the same memory cell block. However, a defective cell in a first memory cell block may not be replaced with a normal cell in a second memory cell block that neighbors the first memory cell block since the data topology is different without a user reprogramming a memory test pattern.